MPC8540 datasheet(488/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-10

Freescale Semiconductor

DUART

12.3.1.5

Interrupt ID Registers (UIIR0, UIIR1)

The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of

interrupt is active. They also indicate if the FIFOs are enabled.

The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR.

The four levels of interrupt conditions in order of priority are:

1. Receiver line status

2. Received data ready/character time-out

3. Transmitter holding register empty

4. MODEM status

See Table 12-11 for more details.

When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates

the highest priority pending interrupt. While this read transaction is occurring, the associated

DUART serial channel records new interrupts, but does not change the contents of UIIR until the

read access is complete.

Figure 12-7 shows the bits in the UIIR.

Table 12-10 describes the fields of the UIIR.

012

3456

—

IID3

IID2

IID1

IID0

Reset

0x01

Offset

0x0_4502, 0x0_4602

Figure 12-7. Interrupt ID Registers (UIIR)

Table 12-10. UIIR Field Definitions

Bits

Name

Description

0–1

FIFOs enabled. Reflects the setting of UFCR[FEN]

2–3

—

Reserved

IID3

Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 12-11. IID3 is

set along with IID2 only when a timeout interrupt is pending for FIFO mode.

5–6

IID2–1 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 12-11.

IID0

IID0 indicates when an interrupt is pending.

0 The UART has an active interrupt ready to be serviced.

1 No interrupt is pending.

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