MPC8540 datasheet(489/1302 Pages) FREESCALE

489 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-11

The bits contained in the UIIR registers are described in Table 12-11.

12.3.1.6

FIFO Control Registers (UFCR0, UFCR1)

The UFCR, a write-only register, is used to enable and clear the receiver and transmitter FIFOs,

set a receiver FIFO trigger level to control the received data available interrupt, and select the type

of DMA signaling.

When the UFCR bits are written, the FIFO enable bit must also be set or else the UFCR bits are

not programmed. When changing from FIFO mode to 16450 mode (non-FIFO mode) and vice

versa, data is automatically cleared from the FIFOs.

After all the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.

Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is

not cleared. Both TFR and RFR are self-clearing bits.

Figure 12-8 shows the bits in the UFCRs.

Table 12-11. UIIR IID Bits Summary

IID Bits

IID[3–0]

Priority

Level

Interrupt Type

Interrupt Description

How To Reset Interrupt

0b0001

—

0b0110

Highest Receiver line status

Overrun error, parity error, framing

error, or break interrupt

Read the line status register.

0b0100

Second Received data available Receiver data available or trigger level

reached in FIFO mode

Read the receiver buffer register or

interrupt is automatically reset if the

number of bytes in the receiver FIFO

drops below the trigger level.

0b1100

Second Character time-out

No characters have been removed

from or input to the receiver FIFO

during the last 4 character times and

there is at least one character in the

receiver FIFO during this time.

Read the receiver buffer register.

0b0010

Third

UTHR empty

Transmitter holding register is empty

Read the UIIR or write to the UTHR.

0b0000

Fourth

MODEM status

CTS input value changed since last

read of UMSR

Read the UMSR.

012

3456

RTL

—

DMS

TFR

RFR

FEN

Reset

0x00

Offset

0x0_4502, 0x0_4602

Figure 12-8. FIFO Control Registers (UFCR0, UFCR1)

MPC8540 Datasheet(PDF) 489 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 489 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL