MPC8540 datasheet(493/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-15

12.3.1.9

Line Status Registers (ULSR0, ULSR1)

The ULSRs are read-only registers that monitor the status of the data transfer on the UART buses.

To isolate the status bits from the proper character received through the UART bus, software

should read the ULSR and then the URBR.

Figure 12-11 shows the bits in the ULSRs.

Table 12-16 describes the fields of the ULSRs.

012

3456

RFE

TEMT

THRE

Reset

0x60

Offset

0x0_4505, 0x0_4605

Figure 12-11. Line Status Register (ULSR)

Table 12-16. ULSR Field Definitions

Bits Name

Description

RFE

Receiver FIFO error

0 This bit is cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no

remaining receiver FIFO errors.

1 Set to one when one of the characters in the receiver FIFO encounters an error (framing, parity, or

break interrupt)

TEMT Transmitter empty

0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode,

a data character is in the transmitter FIFO or the internal transmitter shift register.

1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter

FIFO and the internal transmitter shift register are empty.

THRE Transmitter holding register empty

0 The UTHR is not empty.

1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO

mode, the transmitter FIFO contains no data character.

Break interrupt

0 This bit is cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit

is received).

1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of

time. A break condition is expected to last at least two character lengths and a new character is not

loaded until SIN returns to the mark state (logic 1) and a valid START is detected. In FIFO mode, a

zero character is encountered in the FIFO (the zero character is at the top of the FIFO). In FIFO mode,

only one zero character is stored. Note that the ULSR[BI] is set immediately after ULSR is read if bus

remains zero and no mark state followed by a valid new character has been detected.

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