MPC8540 datasheet(496/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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496 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-18

Freescale Semiconductor

DUART

Figure 12-14 shows the bits in the UAFRs.

Table 12-19 describes the fields of the UAFRs.

12.3.1.13 DMA Status Registers (UDSR0, UDSR1)

The DMA status registers (UDSRs) are read-only registers that return transmitter and receiver

FIFO status. UDSRs also provide the ability to assist DMA data operations to and from the FIFOs.

Figure 12-15 shows the bits in UDSRs.

Reset

0x00

Offset

0x0_4502, 0x0_4602

Figure 12-14. Alternate Function Register (UAFR)

Table 12-19. UAFR Field Definitions

Bits Name

Description

0–5

—

Reserved

Baud clock select

0 The baud clock is not gated off.

1 The baud clock is gated off.

Concurrent write enable

0 Disables writing to both UART0 and UART1

1 Enables concurrent writes to corresponding UART registers. A write to a register in UART0 is also a

write to the corresponding register in UART1 and vice versa.

567

TXRDY RXRDY

Reset

0x01

Offset

0x0_4510, 0x0_4610

Figure 12-15. DMA Status Register (UDSR)

MPC8540 Datasheet(PDF) 496 Page - Freescale Semiconductor, Inc