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MPC8540 Datasheet(PDF) 492 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 492 Page - Freescale Semiconductor, Inc |
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492 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 12-14 Freescale Semiconductor DUART 12.3.1.8 MODEM Control Registers (UMCR0, UMCR1) The UMCRs control the interface with the external peripheral device on the UART bus. Figure 12-10 shows the bits in the UMCRs. Table 12-15 describes the fields of UMCRs. . Table 12-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] PEN SP EPS Parity Selected 000 No parity 001 No parity 010 No parity 011 No parity 1 0 0 Odd parity 1 0 1 Even parity 110 Mark parity 1 1 1 Space parity 0 2 3456 7 R LOOP RTS W Reset 0x00 Offset 0x0_4504, 0x0_4604 Figure 12-10. Modem Control Register (UMCR) Table 12-15. UMCR Field Definitions Bits Name Description 0–2 — Reserved 3 LOOP Local loop-back mode 0 Normal operation 1 Functionally, the data written to UTHR can be read from URBR of the same UART, and UMCR[RTS] is tied to UMSR[CTS]. 4–5 — Reserved 6 RTS Ready to send 0 Negates corresponding UART_RTS output 1 Assert corresponding UART_RTS output. Informs external MODEM or peripheral that the UART is ready for sending/receiving data 7— Reserved |
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