MPC8540 datasheet(490/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-12

Freescale Semiconductor

DUART

Table 12-12 describes the fields of the UFCRs.

12.3.1.7

Line Control Registers (ULCR0, ULCR1)

The ULCRs specify the data format for the UART bus and set the divisor latch access bit

ULCR[DLAB], which controls the ability to access the divisor latch least and most significant bit

registers and the alternate function register.

After initializing the ULCR, the software should not re-write the ULCR when valid transfers on

the UART bus are active. The software should not re-write the ULCR until the last STOP bit has

been received and there are no new characters being transferred on the bus.

The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the

UART bus. The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN]

and ULCR[EPS] help determine the set parity value. See Table 12-14 for more information.

ULCR[NSTB], defines the number of STOP bits to be sent at the end of the data transfer. The

receiver only checks the first STOP bit, regardless of the number of STOP bits selected. The word

length select bits (1 and 0) define the number of data bits that are transmitted or received as a serial

character. The word length does not include START, parity, and STOP bits.

Table 12-12. UFCR Field Definitions

Bits Name

Description

0–1

RTL

Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the

number of bytes in the receiver FIFO equals the designated interrupt trigger level as follows:

00 1 byte

01 4 bytes

10 8 bytes

11 14 bytes

2–3

—

Reserved

DMS

DMA mode select. See Section 12.4.5.2, “DMA Mode Select,” for more information.

0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.

1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.

TFR

Transmitter FIFO reset

0 No action

1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0

RFR

Receiver FIFO reset

0 No action

1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0

FEN

FIFO enable

0 FIFOs are disabled and cleared

1 Enables the transmitter and receiver FIFOs

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