MPC8540 datasheet(495/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-17

Table 12-17 describes the fields of the UMSRs.

12.3.1.11 Scratch Registers (USCR0, USCR1)

The USCR registers are for debugging software or the DUART hardware. The USCRs do not

affect the operation of the DUART.

Figure 12-13 shows the bits in USCRs.

Table 12-18 describes the fields of the USCRs.

12.3.1.12 Alternate Function Registers (UAFR0, UAFR1)

The UAFRs give software the ability to write to both UART0 and UART1 registers simultaneously

with the same write operation. The UAFRs also provide a means for the device’s performance

monitor to track the baud clock.

Table 12-17. UMSR Field Definitions

Bits Name

Description

0–2

—

Reserved

CTS

Clear to send. Represents the inverted value of the CTS input pin from the external peripheral device

0 Corresponding CTSn is negated

1 Corresponding CTSn is asserted. The MODEM or peripheral device is ready for data transfers.

4–6

—

Reserved

DCTS Delta clear to send

0 No change on the corresponding CTSn signal since the last read of UMSR[CTS]

1 The CTSn value has changed, since the last read of UMSR[CTS]. Causes an interrupt if UIER[EMSI]

is set to detect this condition

DATA

Reset

0x00

Offset

0x0_4507, 0x0_4607

Figure 12-13. Scratch Register (USCR)

Table 12-18. USCR Field Definitions

Bits

Name

Description

0–7

DATA

Data

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