MPC8540 datasheet(497/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-19

Table 12-20 describes the fields of the UDSRs.

Table 12-20. UDSR Field Definitions

Bits

Name

Description

0–5

—

Reserved

TXRDY Transmitter ready. This read-only bit reflects the status of the transmitter FIFO or the UTHR. The status

depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.

0 The bit is cleared, as shown in Table 12-22.

1 This bit is set, as shown in Table 12-21.

RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends

on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.

0 The bit is cleared, as shown in Table 12-24.

1 This bit is set, as shown in Table 12-23.

Table 12-21. UDSR[TXRDY] Set Conditions

DMS FEN

DMA Mode

Meaning

TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.

TXRDY is set when the transmitter FIFO is full.

Table 12-22. UDSR[TXRDY] Cleared Conditions

DMS FEN

DMA Mode

Meaning

TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.

TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY

remains clear when the transmitter FIFO is not yet full.

Table 12-23. UDSR[RXRDY] Set Conditions

DMS FEN

DMA Mode

Meaning

RXRDY is set when there are no characters in the receiver FIFO or URBR.

RXRDY is set when the trigger level has not been reached and there has been no time out.

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