MPC8540 datasheet(501/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-23

transmitter SOUT is set to a logic 1 and the receiver SIN is disconnected. The output of the

transmitter shift register is looped back into the receiver shift register input. The CTS (input signal)

is disconnected, RTS is internally connected to CTS, and the RTS (output signal) becomes

inactive. In this diagnostic mode, data that is transmitted is immediately received. In local

loop-back mode the transmit and receive data paths of the DUART can be verified. Note that in

local loop-back mode, the transmit/receive interrupts are fully operational and can be controlled

by the interrupt enable register (UIER).

12.4.4 Errors

The following sections describe framing, parity, and overrun errors which may occur while data is

transferred on the UART bus. Each of the error bits are usually cleared, as described below, when

the line status register (ULSR) is read.

12.4.4.1

Framing Error

When an invalid STOP bit is detected, a framing error occurs and ULSR[FE] is set. Note that only

the first STOP bit is checked. In FIFO mode, ULSR[FE] is set when the character at the top of the

FIFO detects a framing error. An attempt to re-synchronize occurs after a framing error. The

UART assumes that the framing error (due to a logic 0 being read when a logic 1 (STOP) was

expected) was due to a STOP bit overlapping with the next START bit. ULSR[FE] is cleared when

ULSR is read or when a new character is loaded into the URBR from the receiver shift register.

12.4.4.2

Parity Error

A parity error occurs, and ULSR[PE] is set, when unexpected parity values are encountered while

receiving data. In FIFO mode, ULSR[PE] is set when the character with the error is at the top of

the FIFO. ULSR[PE] is cleared when ULSR is read or when a new character is loaded into the

URBR.

12.4.4.3

Overrun Error

When a new (overwriting character) STOP bit is detected and the old character is lost, an overrun

error occurs and ULSR[OE] is set. In FIFO mode, ULSR[OE] is set after the receiver FIFO is full

(despite the receiver FIFO trigger level setting) and a new character has been received into the

internal receiver shift register. Data in the FIFO is not overwritten; only the shift register data is

overwritten. Therefore, the interrupt occurs immediately. ULSR[OE] is cleared when ULSR is

read.

MPC8540 Datasheet(PDF) 501 Page - Freescale Semiconductor, Inc