MPC8540 datasheet(505/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-1

Chapter 13

Local Bus Controller

This chapter describes the local bus controller (LBC) block. It describes the external signals and

the memory-mapped registers as well as a functional description of the general-purpose

chip-select machine (GPCM), SDRAM machine, and user-programmable machines (UPMs) of

the LBC. Finally, it includes an initialization and applications information section with many

specific examples of its use.

13.1 Introduction

Figure 13-1 is a functional block diagram of the LBC, which supports three interfaces: GPCM,

UPM, and SDRAM controller.

Figure 13-1. Local Bus Controller Block Diagram

UPM

CTRL

GPCM

SDRAM

Memory

Controller

Address and

Data Machine

Banks and

Config

Regs

UPM

RAM

Transfer Acknowledge

Local Address

Local Data

Refresh

Timers/

Counters

Local

Memory

Compare

GPCM CTRL

LOE

LGTA

LBCTL

UPM CTRL

LGPL[0:3]

LGPL4/LUPWAIT

LGPL5

SDRAM CTRL

LSDA10

LSDWE

LSDRAS

LSDCAS

LCS[0:7]

LWE[0:3]

LSDDQM[0:3]

LBS[0:3]

LA[27:31]

LDP[0:3]

LALE

Clock

Divider

LAD[0:31]

LPBSE

LCLK

LCKE

LSYNC_IN

LSYNC_OUT

MSRCID[0:4]

MDVAL

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