MPC8540 datasheet(509/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-5

13.2 External Signal Descriptions

Table 13-1 contains a list of external signals related to the LBC and summarizes their function.

Table 13-1. Signal Properties—Summary

Name

Number of

Signals

Direction

Function

LALE

Output

External address latch enable

LCS

Output

Chip selects

LWE/

LSDDQM/

LBS

Output

GPCM mode: write enable

SDRAM mode: byte lane data mask

UPM mode: byte (lane) select

LSDA10/

LGPL0

Output

SDRAM mode: row address

bit/command bit

UPM mode: general-purpose line 0

LSDWE/

LGPL1

Output

SDRAM mode: write enable

UPM mode: general-purpose line 1

LOE/

LSDRAS/

LGPL2

Output

GPCM mode: output enable

SDRAM mode: row address strobe

UPM mode: general-purpose line 2

LSDCAS/

LGPL3

Output

SDRAM mode: column address strobe

UPM mode: general-purpose line 3

LGTA/

LGPL4/

LUPWAIT/

LPBSE

Input

Output

Input

Output

GPCM mode: transaction termination

UPM mode: general-purpose line 4

UPM mode: external device wait

Local bus parity byte select

LGPL5

Output

UPM mode: general-purpose line 5

LBCTL

Output

Data buffer control

LA[27:31]

Output

Local bus non-multiplexed address lsb’s

LAD[0:31]

Input/Output Multiplexed address/data bus

LDP

Input/Output Local bus data parity

LCKE

Output

Local bus clock enable

LCLK[0:2]

Output

Local bus clocks

LSYNC_IN

Input

DLL synchronize input

LSYNC_OUT

Output

DLL synchronize output

MDVAL

Output

In LBC debug mode: local bus data valid

MSRCID

Output

In LBC debug mode: local bus source ID

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