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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-9

13.3 Memory Map/Register Definition

Table 13-3 shows the memory mapped registers of the LBC. Undefined 4-byte address spaces

within offset 0x000–0xFFF are reserved.

MDVAL

O Local bus data valid (LBC debug mode only)

State

Meaning

Asserted/Negated—For a read, MDVAL asserts for one bus cycle in the cycle immediately

preceding the sampling of read data on LAD[0:31]. For a write, MDVAL asserts for one

bus cycle during the final cycle for which the current write data on LAD[0:31] is valid.

During burst transfers, MDVAL asserts for each data beat.

Timing Assertion/Negation—Valid only while the LBC is in system debug mode. In debug mode,

MDVAL asserts when the LBC generates a data transfer acknowledge.

MSRCID[0:4]

O Local bus source ID (LBC debug mode only). In debug mode, all MSRCID[0:4] pins are driven high unless

MSRCID[0:4] is driving a debug source ID for identifying the internal system device controlling the LBC.

State

Meaning

Asserted/Negated—Remain high until the last bus cycle of the assertion of LALE, in which case

the source ID of the address is indicated, or until MDVAL is asserted, in which case the

source ID relating to the data transfer is indicated. In case of address debug,

MSRCID[0:4] is valid only when the address on LAD[0:31] consists of all physical address

bits—with optional padding—for reconstructing the system address presented to the

LBC. For example, MSRCID[0:4] is valid only during CAS phases of SDRAM accesses,

because the column, bank select, and (normally unused) row address bits are all present

on LAD[0:31] during a CAS cycle

Table 13-3. Local Bus Controller Memory Map

Address Offset

Use

Access

Reset

Section/Page

0x0_5000

BR0—Base register 0

R/W

0x0000_nn011

13.3.1.1/13-11

0x0_5008

BR1—Base register 1

0x0000_0000

0x0_5010

BR2—Base register 2

0x0_5018

BR3—Base register 3

0x0_5020

BR4—Base register 4

0x0_5028

BR5—Base register 5

0x0_5030

BR6—Base register 6

0x0_5038

BR7—Base register 7

Table 13-2. Local Bus Controller Detailed Signal Descriptions (continued)

Signal

I/O

Description

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