MPC8540 datasheet(512/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-8

Freescale Semiconductor

Local Bus Controller

LAD[0:31]

I/O Multiplexed address/data bus. For configuration of a port size in BRn[PS] as 32 bits, all of LAD[0:31] must

be connected to the external RAM data bus, with LAD[0:7] occupying the most significant byte lane

(at address offset 0). For a port size of 16 bits, LAD[0:7] connect to the most significant byte lane

(at address offset 0), while LAD[8:15] connect to the least-significant byte lane (at address offset 1);

LAD[16:31] are unused for 16-bit port sizes. For a port size of 8 bits, only LAD[0:7] are connected

to the external RAM.

State

Meaning

Asserted/Negated—LAD[0:31] is the shared 32-bit address/data bus through which external

RAM devices transfer data and receive addresses.

Timing Assertion/Negation—During assertion of LALE, LAD[0:31] are driven with the RAM address for

the access to follow. External logic should propagate the address on LAD[0:31] while

LALE is asserted, and latch the address upon negation of LALE. After LALE is negated,

LAD[0:31] are either driven by write data or are made high impedance by the LBC in order

to sample read data driven by an external device. Following the last data transfer of a

write access, LAD[0:31] are again taken into a high-impedance state.

LDP[0:3]

I/O Local bus data parity. Drives and receives the data parity corresponding with the data phases on

LAD[0:31].

State

Meaning

Asserted/Negated—During write accesses, a parity bit is generated for each 8 bits of

LAD[0:31], such that LDP0 is even/odd parity for LAD[0:7], while LDP3 is even/odd parity

for LAD[24:31]. Unused byte lanes for port sizes less than 32 bits have undefined parity.

Timing Assertion/Negation—Drive and receive the data parity corresponding with the data phases on

LAD[0:31]. For read accesses, the parity bits for each byte lane are sampled on LDP[0:3]

with the same timing that read data is sampled on LAD[0:31]. LDP[0:3] change

impedance in concert with LAD[0:31].

LCKE

O Local bus clock enable

State

Meaning

Asserted/Negated—LCKE is the bus clock enable signal (CKE) for JEDEC-standard SDRAM

devices. Asserted during normal SDRAM operation.

LCLK[0:2]

O Local bus clocks

State

Meaning

Asserted/Negated—LCLK[0:2] drive an identical bus clock signal for distributed loads. If the

LBC DLL is enabled (see LCRR[DBYP], Figure 13-19 on page 13-32), the bus clock

phase is shifted earlier than transitions on other LBC signals (such as LAD[0:31] and

LCSn) by a time delay matching the delay of the DLL timing loop set up between

LSYNC_OUT and LSYNC_IN.

LSYNC_OUT

O DLL synchronization out

State

Meaning

Asserted/Negated—A replica of the bus clock, appearing on LSYNC_OUT, should be

propagated through a passive timing loop and returned to LSYNC_IN for achieving

correct DLL lock.

Timing Assertion/Negation—The time delay of the timing loop should be such that it compensates for

the round-trip flight time of LCLK[0:2] and clocked drivers in the system. No load other

than a timing loop should be placed on LSYNC_OUT.

LSYNC_IN

DLL synchronization in

State

Meaning

Asserted/Negated—See description of LSYNC_OUT.

Table 13-2. Local Bus Controller Detailed Signal Descriptions (continued)

Signal

I/O

Description

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