MPC8540 datasheet(515/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-11

Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to

them has no effect.

13.3.1.1

Base Registers (BR0–BR7)

The base registers (BRn), shown in Figure 13-2, contain the base address and address types for

each memory bank. The memory controller uses this information to compare the address bus value

with the current address accessed. Each register (bank) includes a memory attribute and selects the

machine for memory operation handling. Note that after system reset, BR0[V] is set,

BR1[V]–BR7[V] are cleared, and the value of BR0[PS] reflects the initial port size configured by

the boot ROM location pins.

Table 13-4 describes BRn fields.

17 181920

2627

—

DECC WP

MSEL

ATOM

Reset

0000_0000_0000_0000_000P_S000_0000_0000/1 1

Offset

0x0_5000 (BR0); 0x0_5008 (BR1); 0x0_5010 (BR2); 0x0_5018 (BR3);

0x0_5020 (BR4); 0x0_5028 (BR5); 0x0_5030 (BR6); 0x0_5038 (BR7);

1 BR0 has its valid bit set during reset. Thus bank 0 is valid with the port size (PS) configured from external boot ROM

configuration pins during reset. All other base registers have all bits cleared to zero during reset.

Figure 13-2. Base Registers (BRn)

Table 13-4. BRn Field Descriptions

Bits

Name

Description

0–16

Base address. The upper 17 bits of each base register are compared to the address on the address

bus to determine if the bus master is accessing a memory bank controlled by the memory controller.

Used with the address mask bits ORn[AM].

17–18

—

Reserved

19–20

Port size. Specifies the port size of this memory region. For BR0, PS is configured from the boot ROM

location pins during reset. For all other banks the value is reset to 00 (port size not defined).

00 Reserved

01 8-bit

10 16-bit

11 32-bit

21–22 DECC Specifies the method for data error checking.

00 Data error checking disabled, but normal parity generation

01 Normal parity generation and checking

10 Read-modify-write parity generation and normal parity checking (32-bit port size only)

11 Reserved

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