MPC8540 datasheet(519/1302 Pages) FREESCALE

519 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-15

21–22

ACS

Address to chip-select setup. Determines the delay of the LCSn assertion relative to the address

change when the external memory access is handled by the GPCM. At system reset, OR0[ACS] = 11.

LCRR[CLKDIV]

Value

Meaning

x00

LCSn is output at the same time as the address lines. Note that

this overrides the value of CSNT such that CSNT=0.

Reserved.

210

LCSn is output a half bus clock cycle after the address lines.

4 or 8

LCSn is output a quarter bus clock cycle after the address lines.

LCSn is output a half bus clock cycle after the address lines.

XACS

Extra address to chip-select setup. Setting this bit increases the delay of the LCSn assertion relative

to the address change when the external memory access is handled by the GPCM. After a system

reset, OR0[XACS] = 1.

0 Address to chip-select setup is determined by ORx[ACS] and LCRR[CLKDIV].

1 Address to chip-select setup is extended (see Table 13-23 and Table 13-24 for LCRR[CLKDIV] = 4

or 8, Table 13-25 and Table 13-26 for LCRR[CLKDIV] = 2).

24–27

SCY

Cycle length in bus clocks. Determines the number of wait states inserted in the bus cycle, when the

GPCM handles the external memory access. Thus it is the main parameter for determining cycle

length. The total cycle length depends on other timing attribute settings. After a system reset,

OR0[SCY] = 1111.

0000 No wait states

0001 1 bus clock cycle wait state

...

1111 15 bus clock cycle wait states

SETA

External address termination

0 Access is terminated internally by the memory controller unless the external device asserts LGTA

earlier to terminate the access.

1 Access is terminated externally by asserting the LGTA external pin. (Only LGTA can terminate the

access).

TRLX

Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals.

0 Normal timing is generated by the GPCM.

1 Relaxed timing on the following parameters:

•Adds an additional cycle between the address and control signals (only if ACS

≠ 00)

•Doubles the number of wait states specified by SCY, providing up to 30 wait states

•Works in conjunction with EHTR to extend hold time on read accesses

•LCSn (only if ACS

≠ 00) and LWE signals are negated one cycle earlier during writes.

Table 13-6. ORn

—GPCM Field Descriptions (continued)

Bits

Name

Description

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