MPC8540 datasheet(523/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-19

Table 13-9 describes the MAR field.

13.3.1.4

UPM Mode Registers (MxMR)

The UPM machine mode registers (MAMR, MBMR and MCMR), shown in Figure 13-7, contain

the configuration for the three UPMs.

Table 13-10 describes UPM mode fields.

Table 13-9. MAR Field Description

Bits

Name

Description

0–31

Address that can be output to the address signals under control of the AMX bits in the UPM RAM word.

1718

2526

RFEN

UWPL

G0CL

GPL4

RLF

WLF

TLF

MAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5070 (MAMR); 0x0_5074 (MBMR); 0x0_5078 (MCMR)

Figure 13-7. UPM Mode Registers (MxMR)

Table 13-10. MxMR Field Descriptions

Bits

Name

Description

0—

Reserved

RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh

executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no

refresh services can be provided, even if UPMB and/or UPMC have their RFEN bit set.

0 Refresh services are not required

1 Refresh services are required

2–3

Command opcode. Determines the command executed by the UPMn when a memory access hits a

UPM assigned bank. See Section 13.4.4.2, “Programming the UPMs,” for important programming

considerations.

00 Normal operation

01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents

of the MDR into the RAM location pointed to by MAD. After the access, MAD is automatically

incremented.

10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the

contents of the RAM location pointed to by MAD into the MDR. After the access, MAD is

automatically incremented.

11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in

the RAM array. The pattern run starts at the location pointed to by MAD and continues until the

LAST bit is set in the RAM word.

UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode.

0 LUPWAIT is active high.

1 LUPWAIT is active low.

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