MPC8540 datasheet(525/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-21

13.3.1.5

Memory Refresh Timer Prescaler Register (MRTPR)

The refresh timer prescaler register (MRTPR), shown in Figure 13-8, is used to divide the system

clock to provide the SDRAM and UPM refresh timers clock.

14–17

RLF

Read loop field. Determines the number of times a loop defined in the UPMn will be executed for a

burst- or single-beat read pattern or when MxMR[OP] = 11 (RUN command)

0000 16

0001 1

0010 2

0011 3

...

1110 14

1111 15

18–21

WLF

Write loop field. Determines the number of times a loop defined in the UPMn will be executed for a

burst- or single-beat write pattern.

0000 16

0001 1

0010 2

0011 3

...

1110 14

1111 15

22–25

TLF

Refresh loop field. Determines the number of times a loop defined in the UPMn will be executed for a

refresh service pattern.

0000 16

0001 1

0010 2

0011 3

...

1110 14

1111 15

26–31

MAD

Machine address. RAM address pointer for the command executed. This field is incremented by 1 each

time the UPM is accessed, and the OP field is set to WRITE or READ. Address range is 64 words per

UPMn.

PTP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5084

Figure 13-8. Memory Refresh Timer Prescaler Register (MRTPR)

Table 13-10. MxMR Field Descriptions (continued)

Bits

Name

Description

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