MPC8540 datasheet(522/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-18

Freescale Semiconductor

Local Bus Controller

Table 13-8 describes BRn fields for SDRAM mode.

13.3.1.3

UPM Memory Address Register (MAR)

Figure 13-6 shows the fields of the UPM memory address register (MAR).

Table 13-8. ORn

—SDRAM Field Descriptions

Bits

Name

Description

0–16

SDRAM address mask. Masks corresponding BRn bits. Masking address bits independently allows

external devices of different size address ranges to be used. Address mask bits can be set or cleared

in any order in the field, allowing a resource to reside in more than one area of the address map. AM

can be read or written at any time.

0 Corresponding address bits are masked.

1 The corresponding address bits are used in the comparison with address pins.

17–18

—

Reserved

19–21

COLS

Number of column address lines. Sets the number of column address lines in the SDRAM device.

000 7

001 8

010 9

011 10

100 11

101 12

110 13

111 14

—

Reserved

23–25

ROWS

Number of row address lines. Sets the number of row address lines in the SDRAM device.

000 9

001 10

010 11

011 12

100 13

101 14

110 15

111 Reserved

PMSEL Page mode select. Selects page mode for the SDRAM connected to the memory controller bank.

0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle.

1 Page is kept open until a page miss or refresh occurs.

27–30

—

Reserved

EAD

External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).

0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)

1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified

by LCRR[EADC]).

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5068

Figure 13-6. UPM Memory Address Register (MAR)

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