MPC8540 datasheet(520/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-16

Freescale Semiconductor

Local Bus Controller

13.3.1.2.3 Option Registers (ORn)—UPM Mode

Figure 13-4 shows the bit fields for ORn when the corresponding BRn[MSEL] selects a UPM

machine.

Table 13-7 describes BRn fields for UPM mode.

EHTR

Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between

a read access from the current bank and the next access.

TRLX

EHTR

Meaning

The memory controller generates normal timing. No additional

cycles are inserted.

1 idle clock cycle is inserted.

4 idle clock cycles are inserted.

8 idle clock cycles are inserted.

EAD

External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).

0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)

1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified

by LCRR[EADC]).

181920

22 23 24

BCTLD

TRLX EHTR EAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_5004 (OR0); 0x0_500c (OR1); 0x0_5014 (OR2); 0x0_501c (OR3);

0x0_5024 (OR4); 0x0_502c (OR5); 0x0_5034 (OR6); 0x0_503c (OR7);

Figure 13-4. Option Registers (ORn) in UPM Mode

Table 13-7. ORn

—UPM Field Descriptions

Bits

Name

Description

0–16

UPM address mask. Masks corresponding BRn bits. Masking address bits independently allows

external devices of different size address ranges to be used. Address mask bits can be set or cleared

in any order in the field, allowing a resource to reside in more than one area of the address map.

0 Corresponding address bits are masked.

1 The corresponding address bits are used in the comparison with address pins.

17–18

—

Reserved

Table 13-6. ORn

—GPCM Field Descriptions (continued)

Bits

Name

Description

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