MPC8540 datasheet(507/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-3

•

General-purpose chip-select machine (GPCM)

— Compatible with SRAM, EPROM, FEPROM, and peripherals

— Global (boot) chip-select available at system reset

— Boot chip-select support for 8-, 16-, 32-bit devices

— Minimum 3-clock access to external devices

— Four byte-write-enable signals (LWE[0:3])

— Output enable signal (LOE)

— External access termination signal (LGTA)

•

Three user-programmable machines (UPMs)

— Programmable-array-based machine controls external signal timing with a granularity

of up to one-quarter of an external bus clock period

— User-specified control-signal patterns run when an internal master requests a

single-beat or burst read or write access.

— UPM refresh timer runs a user-specified control signal pattern to support refresh

— User-specified control-signal patterns can be initiated by software

— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and

512 Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes

— Support for 8-, 16-, 32-bit devices

— Page mode support for successive transfers within a burst

— Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-,

8-, 16-, 32-, 64-, 128-, and 256-Mbyte page banks

•

Optional monitoring of transfers between local bus internal masters and local bus slaves

(local bus error reporting)

•

Support for delay-locked loop (DLL) with software-configurable bypass for low frequency

bus clocks

13.1.3 Modes of Operation

The LBC provides one GPCM, one SDRAM machine, and three UPMs for the local bus, with no

restriction on how many of the eight banks (chip selects) can be programmed to operate with any

given machine. When a memory transaction is dispatched to the LBC, the memory address is

compared with the address information of each bank (chip select). The corresponding machine

assigned to that bank (GPCM, SDRAM, or UPM) then takes ownership of the external signals that

control the access and maintains control until the transaction ends. Thus, with the LBC in GPCM,

SDRAM, or UPM mode, only one of the eight chip selects is active at any time for the duration of

the transaction.

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