MPC8540 datasheet(502/1302 Pages) FREESCALE

502 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-24

Freescale Semiconductor

DUART

12.4.5 FIFO Mode

The UARTs use an alternate mode (FIFO mode) to relieve the processor core from excessive

software overhead. The FIFO control register (UFCR) is used to enable and clear the receiver and

transmitter FIFOs and set the FIFO receiver trigger level UFCR[RTL] to control the received data

available interrupt UIER[ERDAI].

The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of

the receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when the transmitter

FIFO is full. When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The

first byte written to UTHR is the first byte onto the UART bus.

12.4.5.1

FIFO Interrupts

In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. When a receive data

time-out occurs there is a maskable interrupt condition (through UIER[ERDAI]). See

Section 12.3.1.4, “Interrupt Enable Register (UIER),” for more details on interrupt enables.

The interrupt ID register (UIIR) indicates if the FIFOs are enabled. Interrupt ID3 UIIR[IID3] bit

is only set for FIFO mode interrupts. The character time-out interrupt occurs when no characters

have been removed from or input to the receiver FIFO during the last four character times and

there is at least one character in the receiver FIFO during this time. The character time-out

interrupt (controlled by UIIR[IID]) is cleared when the URBR is read. See Section 12.3.1.5,

“Interrupt ID Registers (UIIR0, UIIR1),” for more information.

The UIIR[FE] bits indicate if FIFO mode is enabled.

12.4.5.2

DMA Mode Select

The UDSR[RXRDY] bit reflects the status of the receiver FIFO or URBR. In mode 0

(UFCR[DMS] is cleared), UDSR[RXRDY] is cleared when there is at least one character in the

receiver FIFO or URBR and it is set when there are no more characters in the receiver FIFO or

URBR. This occurs regardless of the setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS] and

UFCR[FEN] are set), UDSR[RXRDY] is cleared when the trigger level or a time-out has been

reached and it is set when there are no more characters in the receiver FIFO.

The UDSR[TXRDY] bit reflects the status of the transmitter FIFO or UTHR. In mode 0

(UFCR[DMS] is cleared), UDSR[TXRDY] is cleared when there are no characters in the

transmitter FIFO or UTHR and it is set after the first character is loaded into the transmitter FIFO

or UTHR. This occurs regardless of the setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS]

and UFCR[FEN] are set), UDSR[TXRDY] is cleared when there are no characters in the

transmitter FIFO or UTHR and it is set when the transmitter FIFO is full.

See Section 12.3.1.13, “DMA Status Registers (UDSR0, UDSR1),” for a complete description of

the USDR[RXRDY] and USDR[TXRDY] bits.

MPC8540 Datasheet(PDF) 502 Page - Freescale Semiconductor, Inc