MPC8540 datasheet(485/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

12-7

Figure 12-3 shows the bits in the UTHRs.

Table 12-5 describes the fields of UTHR.

12.3.1.3

Divisor Most and Least Significant Byte Registers

(UDMB and UDLB)

The divisor least significant byte register (UDLB) is concatenated with the divisor most significant

byte register (UDMB) to create the divisor used to divide the input clock into the DUART. The

output frequency of the baud generator is 16 times the baud rate; therefore the desired baud rate =

platform clock frequency / (16

× [UDMB||UDLB]). Equivalently, þþ [UDMB||UDLB:0b0000]þ =

platform clock frequency / desired baud rate. Baud rates that can be generated by specific input

clock frequencies are shown in Table 12-8.

Figure 12-4 shows the bits in the UDMBs.

Table 12-6 describes the fields of UDMB registers.

WDATA

Reset

0x00

Offset

0x0_4500, 0x0_4600

Figure 12-3. Transmitter Holding Registers (UTHR0, UTHR1)

Table 12-5. UTHR Field Definition

Bits

Name

Description

0–7

DATA

Data that is written to UTHR (write only)

UDMB

Reset

0x00

Offset

0x0_4501, 0x0_4601

Figure 12-4. Divisor Most Significant Byte Registers (UDMB0, UDMB1)

Table 12-6. UDMB Field Definition

Bits

Name

Description

0–7

UDMB Divisor most-significant byte

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