MPC8540 datasheet(484/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

12-6

Freescale Semiconductor

DUART

12.3.1 Register Descriptions

The following sections describe the MPC8540 UART0 and UART1 registers.

12.3.1.1

Receiver Buffer Registers (URBR0, URBR1)

These registers contain the data received from the transmitter on the UART buses. In FIFO mode,

when read, they return the first byte received. For FIFO status information, refer to the

UDSR[RXRDY] description.

Except for the case when there is an overrun, URBR returns the data in the order it was received

from the transmitter. Refer to the ULSR[OE] description, Section 12.3.1.9, “Line Status Registers

(ULSR0, ULSR1).” Figure 12-3 shows the receiver buffer registers. Note that these registers have

same offset as the UTHRs.

Figure 12-2 shows the bits in the URBRs.

Table 12-4 describes the fields of URBR.

12.3.1.2

Transmitter Holding Registers (UTHR0, UTHR1)

A write to these 8-bit registers causes the UART devices to transfer 5–8 data bits on the UART bus

in the format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is

placed into the FIFO. The data written to UTHR is the data sent onto the UART bus, and the first

byte written to UTHR will be the first byte onto the bus. UDSR[TXRDY] indicates when the FIFO

is full. Refer to the Table 12-21 and the Table 12-22 for more details.

RDATA

Reset

0x00

Offset

0x0_4500, 0x0_4600

Figure 12-2. Receiver Buffer Registers (URBR0, URBR1)

Table 12-4. URBR Field Definition

Bits

Name

Description

0–7

DATA

Data received from the transmitter on the UART bus (read only)

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