MPC8540 datasheet(764/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-138

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.7.1.3 TBI Interface Mode

Table 14-128 describes the signal configurations required for TBI interface mode.

Clear IEVENT register,

IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IMASK, (Optional)

IMASK[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IADDRn, (Optional)

IADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize GADDRn, (Optional)

GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize RCTRL, (Optional)

RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize DMACTRL, (Optional)

DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize (Empty) Transmit Descriptor ring and fill buffers with Data.

Initialize TBASE,

TBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Initialize (Empty) Receive Descriptor ring and fill with empty buffers.

Initialize RBASE,

RBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Enable Rx and Tx,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Table 14-128. TBI Interface Mode Signal Configuration

TSEC Signals

Frequency [MHz] 125

Voltage[V] 3.3/2.5

TBI Interface

Frequency [MHz] 62.5

Voltage[V] 3.3

Signals

I/O

No. of

Signals

I/O

No. of

Signals

GTX_CLK

TX_CLK

RX_CLK1

TxD[0]

TCG[0]

TxD[1]

TCG[1]

TxD[2]

TCG[2]

TxD[3]

TCG[3]

TxD[4]

TCG[4]

Table 14-127. GMII Mode Register Initialization Steps (continued)

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