MPC8540 datasheet(760/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-134

Freescale Semiconductor

Three-Speed Ethernet Controllers

Perform an MII Mgmt write cycle to the external PHY.

Write to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_00uu_00uu_0u00_0000]

where u is user defined based on desired configuration.

Check to see if MII Mgmt write is complete

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.

Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]

The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00.

Perform an MII Mgmt read cycle of Status Register.

Clear MIIMCOM[Read Cycle].

Set MIIMCOM[Read Cycle].

(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MIIMSTAT register and check bit 10 (AN Done and Link is up)

MIIMSTAT ---> [0000_0000_0000_0000_0000_000_0010_0100]

Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend

Ability)

Check auto-negotiation attributes in the PHY as necessary.

Clear IEVENT register,

IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IMASK, (Optional)

IMASK[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IADDRn, (Optional)

IADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize GADDRn, (Optional)

GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize RCTRL, (Optional)

RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize DMACTRL, (Optional)

DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize (Empty) Transmit Descriptor ring and fill buffers with Data.

Initialize TBASE,

TBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Initialize (Empty) Receive Descriptor ring and fill with empty buffers.

Initialize RBASE,

RBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Enable Rx and Tx,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Table 14-124. MII Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 760 Page - Freescale Semiconductor, Inc

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