MPC8540 datasheet(763/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-137

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the TSEC MII Mgmt bus is idle.

Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY

through the Management interface (overrides configuration signals of the PHY),

MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]

Perform an MII Mgmt write cycle to the external PHY.

Write to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed

Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register 1 to set up the interface

mode selection

MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]

Perform an MII Mgmt write cycle to the external PHY.

Write to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection,

MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]

Perform an MII Mgmt write cycle to the external PHY.

Write to MII Mgmt Control with 16-bit data intended for the external PHY register,

MIIMCON[0000_0000_0000_0000_000u_00u1_0100_0000]

where u is user defined based on desired configuration.

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.

Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]

The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00

Perform an MII Mgmt read cycle of Status Register.

Clear MIIMCOM[Read Cycle].

Set MIIMCOM[Read Cycle].

(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

Read the MIIMSTAT register and check bit 10 (AN Done and Link is up),

MIIMSTAT ---> [0000_0000_0000_0000_0000_000_0010_0100]

Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend

Ability)

Check auto-negotiation attributes in the PHY as necessary.

Table 14-127. GMII Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 763 Page - Freescale Semiconductor, Inc

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