MPC8540 datasheet(766/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-140

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-130 describes the register initializations required to reconfigure the PHY to TBI mode

following initial auto-negotiation.

Table 14-130. TBI Mode Register Initialization Steps

Have the TSECn_GTX_CLK configuration signal pulled high and

EC_MDC signal pulled high for TBI mode.

(TSEC attempts to auto-negotiate after system reset.)

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Initialize MACCFG2,

MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]

(I/F Mode = 2, Full Duplex = 1)

Initialize ECNTRL,

ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]

(This example has Statistics Enable = 1)

Initialize MAC Station Address

MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]

to 02608C:876543, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Initialize MAC Station Address

MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]

to 02608C:876543, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Assign a Physical address to the TBI,

TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]

set to 16, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Setup the MII Mgmt clock speed,

MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0111]

Set source clock divide by 28, for example, to insure that EC_MDC clock speed is not greater than 2.5 MHz.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the TSEC MII Mgmt bus is idle.

Set up the MII Mgmt for a read cycle to TBI Control register (write the TBI address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]

The TBI Control register is at offset address 0x0 from TBIPA.

Perform an MII Mgmt read cycle to verify state of TBI Control Register (Optional)

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the TBI address and Register address placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MIIMSTAT and look for AN Enable and other bit information.

Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register

address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]

The AN Advertisement register is at offset address 0x04 from the TBI’s address. (in this case 0x10)

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