MPC8540 datasheet(770/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-144

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-132 describes the shared signals for the RGMII interface.

Table 14-133 describes the register initializations required to reconfigure the PHY to RGMII mode

following initial auto-negotiation.

RX_ER

COL

CRS

Sum

Table 14-132. Shared RGMII Signals

TSEC Signals

I/O

No. of

Signals

RGMII Signals

I/O

No. of

Signals

Function

EC_MDIO

I/O

EC_MDIO

I/O

Management interface I/O

EC_MDC

Management interface Clock

EC_GTX_CLK12

Reference Clock

Sum

Table 14-133. RGMII Mode Register Initialization Steps

Have the TSECn_GTX_CLK configuration signal pulled low and

EC_MDC signal pulled low for RGMII mode.

TBI Control register’s Auto-negotiation Enable and Reset bits are ignored.

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Initialize MACCFG2,

MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]

(I/F Mode = 2, Full Duplex = 1)

Initialize ECNTRL,

ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]

(This example has RGMII 10-Mbps mode, Statistics Enable = 1)

Table 14-131. RGMII Interface Mode Signal Configuration (continued)

TSEC SIGNALS

Frequency [MHz] 125

Voltage[V] 3.3/2.5

RGMII INRTERFACE

Frequency [MHz] 125

Voltage[V] 2.5

Signals

I/O

No. of

Signals

I/O

No. of

Signals

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