MPC8540 datasheet(774/1302 Pages) FREESCALE

774 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-148

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-135 describes the shared signals for the RTBI interface.

Table 14-136 describes the register initializations required to reconfigure the PHY to RTBI mode

following initial auto-negotiation.

RX_ER

COL

CRS

Sum

Table 14-135. Shared RTBI Signals

TSEC Signals

I/O

No. of

Signals

RTBI Signals

I/O

No. of

Signals

Function

EC_MDIO

I/O

EC_MDIO

I/O

Management interface I/O

EC_MDC

Management interface Clock

EC_GTX_CLK12

Reference Clock

Sum

Table 14-136. RTBI Mode Register Initialization Steps

Have the TSECn_GTX_CLK configuration signal pulled high and

the EC_MDC signal pulled low for RTBI mode.

(TSEC attempts to auto-negotiate after system reset.)

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Initialize MACCFG2,

MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]

(I/F Mode = 2, Full Duplex = 1)

Initialize ECNTRL,

ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]

(This example has Statistics Enable = 1)

Table 14-134. RTBI Interlace Mode Signal Configuration (continued)

TSEC Signals

Frequency [MHz] 125

Voltage[V] 3.3/2.5

RTBI Interface

Frequency [MHz] 62.5

Voltage[V] 2.5

Signals

I/O

No. of

Signals

I/O

No. of

Signals

MPC8540 Datasheet(PDF) 774 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 774 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL