MPC8540 datasheet(775/1302 Pages) FREESCALE

775 / 1302 page

Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-149

Initialize MAC Station Address,

MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]

to 02608C:876543, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Initialize MAC Station Address,

MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]

to 02608C:876543, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Assign a Physical address to the TBI,

TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]

set to 16, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Setup the MII Mgmt clock speed,

MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0111]

Set source clock divide by 28, for example, to insure that EC_MDC clock speed is not greater than 2.5 MHz.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the TSEC MII Mgmt bus is idle.

Set up the MII Mgmt for a read cycle to TBI Control register (write the TBI’s address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]

The TBI Control register is at offset address 0x0 from TBIPA.

Perform an MII Mgmt read cycle to verify state of TBI Control Register(0ptional)

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the TBI address and Register address placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MIIMSTAT and look for AN Enable and other bit information.

Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register

address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]

The AN Advertisement register is at offset address 0x04 from the TBI’s address. (in this case 0x10)

Perform an MII Mgmt write cycle to TBI.

Write to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,

MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]

This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half

Duplex mode.

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]

The Control register is at offset address 0x00 from the TBI’s address. (in this case 0x10)

Perform an MII Mgmt write cycle to TBI.

Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,

MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]

This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.

Table 14-136. RTBI Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 775 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 775 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL