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MPC8540 Datasheet(PDF) 779 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 779 Page - Freescale Semiconductor, Inc |
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779 / 1302 page ![]() Introduction MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 15-1 Chapter 15 DMA Controller This chapter describes the DMA controller of this device. 15.1 Introduction The DMA controller transfers blocks of data between the RapidIO controller, PCI, the local bus controller (LBC) interface, and the local address space, independent of the e500 core or external hosts. 15.1.1 Block Diagram Figure 15-1 shows the block diagram of the DMA controller. Figure 15-1. DMA Block Diagram 15.1.2 Overview The DMA controller has four high-speed DMA channels. Both the e500 core and external devices can initiate DMA transfers. All channels are capable of complex data movement and advanced CHN 0 CHN 1 CHN 2 CHN 3 Arbitration and Bandwidth Control Source Controls Destination Controls Address Address Address Controls Tenure Data Controls Tenure Address Interface Data Interface DMA Controller |
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