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MPC8540 Datasheet(PDF) 781 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 781 Page - Freescale Semiconductor, Inc |
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781 / 1302 page  Introduction MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 15-3 • External control capability: This allows an external agent to start, pause, and check the status of a DMA transfer which has already been initialized. • Channel continue capability: The channel continue capability allows software the flexibility of having the DMA controller start with descriptors that have already been programmed while software continues to build more descriptors in memory. • Channel abort capability: The software can abort a previously initiated transfer by setting the bit MRn[CA]. The DMA controller terminates all outstanding transfers initiated by the channel without generating any errors before entering an idle state. Table 15-2 describes bit settings required for each DMA mode of operation Table 15-1. Relationship of Modes and Features Mode Mode with One Additional Feature Mode with Two Additional Features B (Basic) BD (Basic direct) BDS (BD single-write start) BDE (BD external control) BC (Basic chaining) BCE (BC external control) BCS (BC single-write start) Ext (Extended) ExtD (Extended direct) ExtDS (ExtD single-write start) ExtDE (ExtD external control) ExtC (Extended chaining) ExtCE (ExtC external control) ExtCS (ExtC single-write start) Table 15-2. DMA Mode Field Descriptions Modes with Features MRn[XFE] MRn[CTM] MRn[SRW] MRn[EM] MRn[CDSM/SWSM] MRn[EMS_EN] Basic Direct Modes Basic direct 0 1 0 0 0 0 Basic direct external control 0 1 0 0 0 1 Basic direct single-write start 0 1 1 0 1 or 0 0 Basic Chaining Modes Basic chaining 0 0 Reserved 0 0 0 Basic chaining external control 0 0 Reserved 0 0 1 Basic chaining single-write start 0 0 Reserved 0 1 0 Extended Direct Modes Extended direct 1 1 0 0 0 0 Extended direct external control 1 1 0 0 0 1 Extended direct single-write start 11 10 1 or 0 0 |
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