MPC8540 datasheet(785/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-7

15.3.1 Module Memory Map

Figure 15-4 shows the address map of DMA register space.

Figure 15-4. DMA Register Space (Memory-Mapped)

Table 15-4 lists the DMA registers.

Table 15-4. DMA Register Summary

Offset

Access

Reset

Section/Page

General Registers

0x2_1100

MR0—DMA mode register 0

R/W

0x0000_0000

15.3.2.1/15-10

0x2_1104

SR0—DMA status register 0

Special

0x0000_0000

15.3.2.2/15-13

0x2_1108

Reserved

—

0x2_110C

CLNDAR0—DMA current link descriptor address

R/W

0x0000_0000

15.3.2.3/15-14

0x2_1110

SATR0—DMA source attributes register 0

R/W

0x0000_0000

15.3.2.4/15-16

0x2_1114

SAR0—DMA source address register 0

R/W

0x0000_0000

15.3.2.5/15-18

0x2_1118

DATR0—DMA destination attributes register 0

R/W

0x0000_0000

15.3.2.6/15-19

0x2_111C

DAR0—DMA destination address register 0

R/W

0x0000_0000

15.3.2.7/15-21

0x2_1120

BCR0—DMA byte count register 0

R/W

0x0000_0000

15.3.2.8/15-23

0x2_1124

Reserved

—

0x2_1128

NLNDAR0—DMA next link descriptor address register 0

R/W

0x0000_0000

15.3.2.9/15-23

0x2_112C

–

0x2_1130

Reserved

—

General DMA Registers

0x2_1000

0x2_1300

0x2_1FFF

Reserved

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