MPC8540 datasheet(787/1302 Pages) FREESCALE

787 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-9

0x2_1218

DATR2—DMA destination attributes register 2

R/W

0x0000_0000

15.3.2.6/15-19

0x2_121C

DAR2—DMA destination address register 2

R/W

0x0000_0000

15.3.2.7/15-21

0x2_1220

BCR2—DMA byte count register 2

R/W

0x0000_0000

15.3.2.8/15-23

0x2_1224

Reserved

—

0x2_1228

NLNDAR2—DMA next link descriptor address register 2

R/W

0x0000_0000

15.3.2.9/15-23

0x2_122C

–

0x2_1230

Reserved

—

0x2_1234

CLSDAR2—DMA current list alternate base descriptor

address register 2

R/W

0x0000_0000

15.3.2.10/15-24

0x2_1238

Reserved

—

0x2_123C

NLSDAR2—DMA next list descriptor address register 2

R/W

0x0000_0000

15.3.2.11/15-25

0x2_1240

SSR2—DMA source stride register 2

R/W

0x0000_0000

15.3.2.12/15-25

0x2_1244

DSR2—DMA destination stride register 2

R/W

0x0000_0000

15.3.2.13/15-26

0x2_1248

–

0x2_127C

Reserved

—

0x2_1280

MR3—DMA mode register 3

R/W

0x0000_0000

15.3.2.1/15-10

0x2_1284

SR3—DMA status register 3

Special

0x0000_0000

15.3.2.2/15-13

0x2_1288

Reserved

—

0x2_128C

CLNDAR3—DMA current link descriptor address

R/W

0x0000_0000

15.3.2.3/15-14

0x2_1290

SATR3—DMA source attributes register 3

R/W

0x0000_0000

15.3.2.4/15-16

0x2_1294

SAR3—DMA source address register 3

R/W

0x0000_0000

15.3.2.5/15-18

0x2_1298

DATR3—DMA destination attributes register 3

R/W

0x0000_0000

15.3.2.6/15-19

0x2_129C

DAR3—DMA destination address register 3

R/W

0x0000_0000

15.3.2.7/15-21

0x2_12A0

BCR3—DMA byte count register 3

R/W

0x0000_0000

15.3.2.8/15-23

0x2_12A4

Reserved

—

0x2_12A8

NLNDAR3—DMA next link descriptor address register 3

R/W

0x0000_0000

15.3.2.9/15-23

0x2_12AC

–

0x2_12B0

Reserved

—

0x2_12B4

CLSDAR3—DMA current list alternate base descriptor

address register 3

R/W

0x0000_0000

15.3.2.10/15-24

0x2_12B8

Reserved

—

0x2_12BC

NLSDAR3—DMA next list descriptor address register 3

R/W

0x0000_0000

15.3.2.11/15-25

0x2_12C0

SSR3—DMA source stride register 3

R/W

0x0000_0000

15.3.2.12/15-25

0x2_12C4

DSR3—DMA destination stride register 3

R/W

0x0000_0000

15.3.2.13/15-26

Table 15-4. DMA Register Summary (continued)

Offset

Access

Reset

Section/Page

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