MPC8540 datasheet(791/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-13

15.3.2.2 Status Registers (SRn)

The status registers, shown in Figure 15-6, report various DMA conditions during and after a

DMA transfer.

Figure 15-6. Status Registers (SRn)

Table 15-6 describes the bits of the SRn.

Channel continue. This bit applies only to chaining mode and is cleared by hardware after the first

descriptor read when continuing a transfer. This bit is reserved for external master mode.

0No effect.

1 The DMA transfer restarts the transferring process starting at the current descriptor address.

Channel start. This bit is also automatically set by hardware during single-write start mode and external

master start enable mode.

0 Halt the DMA process if channel is busy (SRn[CB] is set). No effect if the channel is not busy.

1 Start the DMA process if channel is not busy (CB is cleared). If the channel was halted (CS = 0 and

CB = 1), the transfer continues from the point at which it was halted.

24 25 26

R 0 00 00000000 00000000 0000

0CH

PE EOLNI

EOSI EOLSI

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1104, 0x2_1184, 0x2_1204, 0x2_1284

Table 15-6. SRn Field Descriptions

Bits

Name

Description

0–23

—

Reserved

Transfer error (Bit reset, write 1 to clear)

0 No error condition during the DMA transfer.

1 Error condition during the DMA transfer. See Section 15.4.3, “DMA Errors” for additional

information.

—

Reserved

Channel halted. Cleared automatically by hardware if MRn[CS] is set again for resuming a halted

transfer.

0 Channel is not halted. If software attempts to halt an idle channel (SRn[CB] is cleared), this bit will

remain 0.

1 DMA transfer was successfully halted by software and it can be resumed.

Programming error (Bit reset, write 1 to clear)

0 No programming error detected.

1 A programming error is detected that prevents the DMA transfer from occurring.

Table 15-5. MRn Field Descriptions (continued)

Bits

Name

Description

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