MPC8540 datasheet(793/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-15

Figure 15-7. Basic Chaining Mode Flow Chart

After the current descriptor is processed, the current link descriptor address register is loaded from

the next link descriptor address register and NLNDARn[EOLND] in the next link descriptor

address register is examined. If EOLND is zero, the DMA controller reads in the new current link

descriptor for processing. If EOLND is set, the last descriptor of the list was just completed. If

extended chaining mode is not enabled, all DMA transfers are complete and the DMA controller

halts.

If extended chaining mode is enabled, the DMA controller examines the state of

NLSDARn[EOLSD] in the next list descriptor address register. If EOLSD is clear, the controller

loads the contents of the next list descriptor address register into the current list descriptor address

complete and the DMA controller halts.

Software initializes CLNDARn with 1st link descriptor.

1st link descriptor is processed.

Current link descriptor

← Next link descriptor.

NLNDARn[EOLND]

set?

Extended Chaining

enabled?

Last link descriptor has been processed.

Done — DMA halts.

NLSDARn[EOLSD]

set?

CLSDARn

← NLSDARn

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