MPC8540 datasheet(794/1302 Pages) FREESCALE

794 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-16

Freescale Semiconductor

DMA Controller

Figure 15-8 shows CLNDARn.

Figure 15-8. Current Link Descriptor Address Registers (CLNDARn)

Table 15-7 describes the fields of the CLNDARn.

15.3.2.4 Source Attributes Registers (SATRn)

The source attributes registers, shown in Figure 15-9, contain the transaction attributes to be used

for the DMA operation. Stride mode is enabled by setting SATRn[SSME]. Source read transaction

type is specified using the SREADTTYPE field.

ATMU bypass mode is enabled by setting SATRn[SBPATMU]. ATMU bypass mode is only

applicable for accesses to RapidIO. If SBPATMU is set, STRANSINT must be set to RapidIO and

attributes that would otherwise come from the ATMU must be specified in this register. If

SBPATMU is not set, attributes are derived from local access windows and outbound ATMU

registers according to the transaction address.

26 27

29 30 31

CLNDA

EOSIE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_110C, 0x2_118C, 0x2_120C, 0x2_128C

Table 15-7. CLNDARn Field Descriptions

Bits

Name

Description

0–26

CLNDA Current link descriptor address. Contains the current descriptor address of the buffer descriptor in

memory. The descriptor must be aligned to a 32-byte boundary.

—

Reserved

EOSIE

End-of-segment interrupt enable

0 Do not generate an interrupt upon completion of the current DMA transfer for the current link

descriptor.

1 Generate an interrupt upon completion of the current DMA transfer for the current link descriptor.

29–31

—

Reserved

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