MPC8540 datasheet(790/1302 Pages) FREESCALE

790 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-12

Freescale Semiconductor

DMA Controller

—

Reserved

SRW

Single register write (Direct mode only; reserved for chaining mode.)

0 Normal operation.

1 Enable a write to the source address register to simultaneously set MRn[CS], starting a DMA transfer,

when MRn[CDSM/SWSM] is also set. Setting this bit and clearing CDSM/SWSM causes a write to the

destination address register to simultaneously set MRn[CS], starting a DMA transfer.

EOSIE

End-of-segments interrupt enable

0 Do not generate an interrupt at the completion of a data transfer. CLNDARn[EOSIE] overrides this bit

on a link descriptor basis.

1 Generate an interrupt at the completion of a data transfer (That is, SRn[EOSI] is set). This bit overrides

the CLNDARn[EOSIE].

EOLNIE

End-of-links interrupt enable

0 Do not generate an interrupt at the completion of a list of DMA transfers.

1 Generate an interrupt at the completion of a list of DMA transfers (That is, NLNDARn[EOLND] is set).

EOLSIE

End-of-lists interrupt enable

0 Do not generate an interrupt at the completion of all DMA transfers.

1 Generate an interrupt at the completion of all DMA transfers (That is, NLNDARn[EOLND] and

NLSDARn[EOLSD] are set).

EIE

Error interrupt enable

0 Do not generate an interrupt if a programming or transfer error is detected.

1 Generate an interrupt if a programming or transfer error is detected.

XFE

Extended features enable

0 Disable the new chaining features.

1 Enable the new chaining features.

CDSM/

SWSM

• In chaining mode: Current descriptor start mode/single-write start mode.

• In basic mode (MRn[XFE] is cleared), setting this bit causes a write to the current link descriptor

address register to simultaneously set MRn[CS], starting a DMA transfer.

• In extended chaining mode (MRn[XFE] is set), setting this bit causes a write to the current list

descriptor address register to simultaneously set MRn[CS], starting a DMA transfer.

• In direct mode: Setting this bit and MRn[SRW] causes a write to the source address register to

simultaneously set MRn[CS], starting a DMA transfer. Clearing this bit and setting MRn[SRW] causes

a write to the destination address register to simultaneously set MRn[CS], starting a DMA transfer. This

bit must be cleared when MRn[SRW] is cleared.

Channel abort

0No effect.

1 Cause the current transfer to be aborted and SRn[CB] to be cleared if the channel is busy. The channel

remains in the idle state until a new transfer is programmed.

CTM

Channel transfer mode

0 Configure the channel in chaining mode.

1 Configure the channel into direct mode. This means that software is responsible for placing all the

required parameters into necessary registers to start the DMA process.

Table 15-5. MRn Field Descriptions (continued)

Bits

Name

Description

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