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MPC8540 Datasheet(PDF) 788 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 788 Page - Freescale Semiconductor, Inc |
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788 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 15-10 Freescale Semiconductor DMA Controller 15.3.2 DMA Register Descriptions The following sections describe the DMA registers. The majority of these registers are channel-specific and can be identified by one of the four offsets that describe the register. 15.3.2.1 Mode Registers (MRn) The mode register allows software to start a DMA transfer and to control various DMA transfer characteristics. Figure 15-5 describes the MRn. Figure 15-5. DMA Mode Registers (MRn) 0x2_12C8 – 0x2_12FC Reserved — — — 0x2_1300 DGSR—DMA general status register Read 0x0000_0000 15.3.2.14/15-26 0 3 4 7 8 9 10 11 12 13 14 15 R0 0 0 0 BWC 00 EMP_EN 00 EMS_EN DAHTS W Reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SAHTS DAHE SAHE 0 SRW EOSIE EOLNIE EOLSIE EIE XFE CDSM/ SWSM CA CTM CC CS W Reset 0000_0000_0000_0000 Offset 0x2_1100, 0x2_1180, 0x2_1200, 0x2_1280 Table 15-4. DMA Register Summary (continued) Offset Register Access Reset Section/Page |
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