MPC8540 datasheet(784/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-6

Freescale Semiconductor

DMA Controller

15.2.2 Detailed Signal Descriptions

Table 15-3 describes the DMA signals.

15.3 Memory Map/Register Definition

This section provides a detailed description of all accessible DMA memory and registers. The

descriptions include individual bit level descriptions and reset states of each register.

Table 15-3. DMA Signals—Detailed Signal Descriptions

Signal

I/O

Description

DMA_DREQn

DMA request

DMA request. The DMA request signal indicates the start of a DMA transfer or a restart from a

paused request. The falling edge of DMA_DREQn causes MRn[CS] to be set, thereby

activating the corresponding DMA channel.

State

Meaning

Asserted—Assertion of DMA_DREQn while DMA_DACKn is negated causes a new

transfer to start OR resumes a paused transfer if the EMP_EN bit is set.

Assertion while DMA_DACKn is asserted results in an illegal condition

Negated—Negation while DMA_DACKn is asserted has no effect. Negation before

the assertion of DMA_DACKn results in an illegal condition

Timing Assertion—Can be asserted asynchronously

Negation— Must remain asserted at least until the assertion of the corresponding

DMA_DACKn

DMA acknowledge. Indicates that a DMA transfer is currently in progress

State

Meaning

Asserted—Indicates that a DMA transfer is currently in progress. Asserted after the

assertion of DMA_DREQ to indicate the start of a transfer

Negated—Negated after finishing a complete transfer or after entering a paused

state if MRn[EMP_EN] is set

Timing Assertion—Asynchronous assertion; asserted for more than three system clocks

Negation—Asynchronous negation; negated for more than three system clocks

DMA_DDONEn

DMA done. Indicates that a DMA transfer is complete.

State

Meaning

Asserted—Indicates transfer completion. SRn[CB] is clear. Note, however, that write

data may still be queued at the target interface or in the process of transfer on

an external interface.

Negated—Indicates that the current transfer is in process

Timing Assertion—Always asserts asynchronously after the negation of the final

DMA_DACKn to indicate completion of a transfer. For a paused transfer,

DMA_DDONEn is asserted asynchronously after the negation of the final

DMA_DACKn.

Negation—Negated asynchronously after the assertion of DMA_DREQn for the next

transfer

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