MPC8540 datasheet(780/1302 Pages) FREESCALE

780 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-2

Freescale Semiconductor

DMA Controller

transaction chaining. Figure 15-1 is a high-level block diagram of the DMA controller. Operations

such as descriptor fetches and block transfers are initiated by each channel. A channel is selected

by the arbitration logic and information is passed to the source and destination control blocks for

processing. The source and destination blocks generate read and write requests to the address

tenure engine, which manages the DMA master port address interface. After a transaction is

accepted by the master port, control is transferred to the data tenure engine that manages the read

and write data transfers. A channel remains active in the shared resources for the duration of the

data transfer unless the allotted bandwidth per channel is reached.

15.1.3 Features

The DMA controller offers the following features:

•

Four high-speed/high-bandwidth channels accessible by local and remote masters

•

Basic DMA operation modes (direct, simple chaining)

•

Extended DMA operation modes (advanced chaining and stride capability)

•

Cascading descriptor chains

•

Misaligned transfers

•

Programmable bandwidth control between channels

•

Up to 256 bytes for DMA sub-block transfers to maximize performance over the RapidIO

interface

•

Three priority levels supported for source and destination transactions

•

Interrupt on error and completed segment, list, or link

•

Externally-controlled transfer using DMA_DREQ, DMA_DACK, and DMA_DDONE

15.1.4 Modes of Operation

The MPC8540 has two modes of operation: basic and extended. Basic mode is the DMA legacy

mode. It does not support advanced features. Extended mode supports advanced features like

striding and flexible descriptor structures.

These two basic modes allow users to initiate and end DMA transfers in various ways. Table 15-1

summarizes the relationship between the modes and the following features:

•

Direct mode. No descriptors are involved. Software must initialize the required fields as

described in Table 15-2 before starting a transfer.

•

Chaining mode. Software must initialize descriptors in memory and the required fields as

described in Table 15-2 before starting a transfer.

•

Single-write start mode. The DMA process can be started by using a single-write command

to either the descriptor address register in one of the chaining modes or the

source/destination address registers in one of the direct modes.

MPC8540 Datasheet(PDF) 780 Page - Freescale Semiconductor, Inc

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