MPC8540 datasheet(776/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-150

Freescale Semiconductor

Three-Speed Ethernet Controllers

Check to see if MII Mgmt write is complete.

Read MII Mgmt Indicator register and check for Busy = 0,

MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]

This indicates that the write cycle was completed.

Check to see if PHY has completed Auto-Negotiation.

Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),

MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]

The Phy Status control register is at address 0x1 and in this case the PHY Address is 0x10.

Perform an MII Mgmt read cycle of Status Register.

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MIIMSTAT register and check bit 10 (AN Done)

MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]

Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend

Ability)

Perform an MII Mgmt read cycle of AN Expansion Register.

Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)

MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]

Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)

Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),

When MIIMIND[BUSY]=0,

read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)

MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_x110_0000]

Clear IEVENT register,

IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IMASK (Optional)

IMASK[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IADDRn (Optional)

IADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize GADDRn (Optional)

GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize RCTRL (Optional)

RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize DMACTRL (Optional)

DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Table 14-136. RTBI Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 776 Page - Freescale Semiconductor, Inc

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