MPC8540 datasheet(772/1302 Pages) FREESCALE

772 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-146

Freescale Semiconductor

Three-Speed Ethernet Controllers

Perform an MII Mgmt read cycle of Status Register.

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (2) and Register address (2) placed in MIIMADD register)

When MIIMIND[BUSY]=0,

read the MIIMSTAT register and check bit 10. (AN Done)

MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]

Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend

Ability)

Perform an MII Mgmt read cycle of AN Expansion Register.

Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)

When MIIMIND[BUSY]=0,

read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)

MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]

Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)

Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]

Clear MIIMCOM[Read Cycle]

Set MIIMCOM[Read Cycle]

(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)

When MIIMIND[BUSY]=0,

read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)

MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_x110_0000]

Clear IEVENT register,

IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IMASK (Optional)

IMASK[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IADDRn (Optional)

IADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize GADDRn (Optional)

GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize RCTRL (Optional)

RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize DMACTRL (Optional)

DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize (Empty) Transmit Descriptor ring and fill buffers with Data

Initialize TBASE,

TBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Initialize (Empty) Receive Descriptor ring and fill with empty buffers

Initialize RBASE,

RBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Enable Rx and Tx,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

Table 14-133. RGMII Mode Register Initialization Steps (continued)

MPC8540 Datasheet(PDF) 772 Page - Freescale Semiconductor, Inc

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