MPC8540 datasheet(789/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-11

Table 15-5 describes the MRn fields.

Table 15-5. MRn Field Descriptions

Bits

Name

Description

0–3

—

Reserved

4–7

BWC

Bandwidth/pause control. Defined only if multiple channels are executing transfers concurrently or if

MRn[EMP_EN] is set. Determines how many bytes a given channel is allowed to transfer before the DMA

engine switches to the next channel. The DMA channel pauses during this switch if MRn[EMP_EN] is set

for this channel.

0000 1 byte

0001 2 bytes

0010 4 bytes

0011 8 bytes

0100 16 bytes

0101 32 bytes

0110 64 bytes

0111 128 bytes

1000 256 bytes

1001 512 bytes

1010 1024 bytes

1011–1110 Reserved

1111 Disable bandwidth sharing to allow

uninterrupted transfers from each channel.

8–9

—

Reserved

EMP_EN External master pause enable. Valid only if MRn[EMS_EN] is set.

0 Disable the channel from being paused by an external master.

1 Enable the channel to be paused by an external master.

11–12

—

Reserved

EMS_EN External master start enable. This bit does not apply to single-write start modes (direct or chaining).

0 Disable the channel from being started by an external DMA start pin.

1 Enable the channel to be started by an external DMA start pin, which sets MRn[CS].

14–15

DAHTS

Destination address hold transfer size. Indicates the transfer size used for each transaction while

MRn[DAHE] is set. The byte count register must be in multiples of the size and the destination address

or smaller than that assigned to MRn[BWC] to avoid undefined behavior.

00 1 byte

01 2 bytes

10 4 bytes

11 8 bytes

16–17

SAHTS

Source address hold transfer size. Indicates the transfer size used for each transaction while MRn[SAHE]

is set. The byte count register must be in multiples of the size and the source address register must be

aligned based on the size. The transfer size assigned to MRn[SAHTS] must be equal to or smaller than

that assigned to MRn[BWC] to avoid undefined behavior.

00 1 byte

01 2 bytes

10 4 bytes

11 8 bytes

DAHE

Destination address hold enable

0 Disable destination address hold.

1 Enable the DMA controller to hold the destination address of a transfer to the size specified by

MRn[DAHTS]. Hardware only supports aligned transfers for this feature.

SAHE

Source address hold enable

0 Disable source address hold.

1 Enable the DMA controller to hold the source address of a transfer to the size specified by

MRn[SAHTS]. Hardware only supports aligned transfers for this feature.

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