MPC8540 datasheet(792/1302 Pages) FREESCALE

792 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-14

Freescale Semiconductor

DMA Controller

15.3.2.3 Current Link Descriptor Address Registers (CLNDARn)

Current link descriptor address registers contain the address of the current link descriptor. In basic

chaining mode, shown in Figure 15-7, software must initialize this register to point to the first link

descriptor in memory.

EOLNI End-of-links interrupt. After transferring the last block of data in the last link descriptor, if MRn[EOLSIE]

is set, then this bit is set and an interrupt is generated.

(Bit reset, write 1 to clear)

Channel busy

0 DMA transfer is finished, an error occurred, or a channel abort occurred.

1 A DMA transfer is currently in progress.

EOSI

End-of-segment interrupt. In chaining mode, after finishing a data transfer, if MRn[EOSIE] is set or if

CLNDARn[EOSIE] is set, this bit gets set and an interrupt is generated. In direct mode, if MRn[EOSIE]

is set, this bit gets set and an interrupt is generated.

(Bit reset, write 1 to clear)

EOLSI End-of-list interrupt. After transferring the last block of data in the last list descriptor, if MRn[EOLSIE]

is set, then this bit is set and an interrupt is generated.

(Bit reset, write 1 to clear)

Table 15-6. SRn Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 792 Page - Freescale Semiconductor, Inc