MPC8540 datasheet(796/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-18

Freescale Semiconductor

DMA Controller

15.3.2.5 Source Address Registers (SARn)

The source address registers, shown in Figure 15-10, contain the address from which the DMA

controller reads data. In direct mode, if MRn[CDSM/SWSM] and MRn[SRW] are set, a write to

this register simultaneously sets MRn[CS], starting a DMA transfer. Software must ensure that this

is a valid address.

Figure 15-10. Source Address Registers (SARn)

Table 15-9 describes the field of the SARn.

12–15

SREADTTYPE DMA source transaction type. Reserved values will result in a programming error being

detected and logged in SR[PE].

• Transaction type to run on RapidIO interface in ATMU bypass mode

0000–0001 Reserved

0010 I/O read home

0011 Reserved

0100 nread

0101–0110 Reserved

0111 maintenance read

1000–1111 Reserved

• Transaction type to run on local address space - used even in non-ATMU bypass mode

0000–0001 Reserved

0011 Reserved

0100 Read, don’t snoop local processor

0101 Read, snoop local processor

0111 Read, unlock L2 cache line

1000–1111 Reserved

16–21

—

Reserved

22–31

ESAD

Extended source address. ESAD[0–7] represent the target ID. ESAD[8–9] represent the two

high-order bits of the local device offset over the RapidIO interface.

Applicable only to RapidIO interface, while SATRn[SBPATMU] is set.

SAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1114, 0x2_1194, 0x2_1214, 0x2_1294

Table 15-8. SATRn Field Descriptions (continued)

Bits

Name

Description

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