MPC8540 datasheet(799/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-21

15.3.2.7 Destination Address Registers (DARn)

The destination address registers, shown in Figure 15-13, contain the addresses to which the DMA

controller writes data.

In direct mode, if MRn[SRW] is set and MRn[CDSM/SWSM] is cleared, a write to this register

simultaneously sets MRn[CS], starting a DMA transfer. Software must ensure that this is a valid

address.

Figure 15-13. Destination Address Registers (DARn)

12–15

DWRITETTYPE DMA destination transaction type. Reserved values will result in a programming error being

detected and logged in SR[PE].

• Transaction type to run on RapidIO interface in ATMU bypass mode

0000 Reserved

0001 Flush

0010 Reserved

0011 SWRITE for all but last, NWRITE_R for last transaction

0100 NWRITE for all but last, NWRITE_R for last transaction

0101 NWRITE_R

0110 Message of size 8, 16, 32, 64, 128 or 256 bytes. (Other message sizes produce

boundedly undefined behavior.)

0111 MAINTENANCE write

1000–1111Reserved

• Transaction type to run on local address space—Used even in non-ATMU bypass mode

0000–0011Reserved

0100 Write, don’t snoop local processor

0101 Write, snoop local processor

0110 Write, allocate L2 cache line

0111 Write, allocate and lock L2 cache line

1000–1111 Reserved

16–21

—

Reserved

22–31

EDAD

Extended destination address. Applicable only for RapidIO interface with DATRn[DBPATMU]

set. EDAD[0–7] represents the RapidIO target ID. EDAD[8–9] is defined as follows, subject

to the transaction type:

Message: EDAD[8–9] represents the value for the mbox field in the message packet.

Other: EDAD[8–9] represents the two high-order bits of the local device offset.

DAD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_111C, 0x2_119C, 0x2_121C, 0x2_129C

Table 15-11. DATRn Field Descriptions (continued)

Bits

Name

Description

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