MPC8540 datasheet(803/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-25

15.3.2.11 Next List Descriptor Address Registers (NLSDARn)

The next list descriptor address register, shown in Figure 15-18, contains the address for the next

list descriptor in memory. If the contents are transferred to the current list descriptor address

Figure 15-18. Next List Descriptor Address Registers (NLSDARn)

Table 15-17 describes the fields of the NLSDARn.

15.3.2.12 Source Stride Registers (SSRn)

The source stride register, shown in Figure 15-19, contains the stride size and distance. Note that

the source stride information is loaded when a new list descriptor is read from memory. Therefore,

the source stride register is applicable for all link descriptors in the new list. Changing the source

stride information for a link requires that a new list be generated.

Figure 15-19. Source Stride Registers (SSRn)

26 27

NLSDA

0000 EOLSD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_113C, 0x2_11BC, 0x2_123C, 0x2_12BC

Table 15-17. NLSDARn Field Descriptions

Bits

Name

Description

0–26

NLSDA

Next list descriptor address. Contains the next descriptor address of the buffer descriptor in

memory. The descriptor must be aligned on a 32-byte boundary.

27–30

—

Reserved

EOLSD

End-of-lists descriptor. This bit is ignored in direct mode.

0 This list descriptor is not the last list descriptor in memory.

1 This list descriptor is the last list descriptor in memory. If this bit is set, then the DMA controller

halts after the last link descriptor transaction is finished.

R 0 0000

SSS

SSD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1140, 0x2_11C0, 0x2_1240, 0x2_12C0

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