MPC8540 datasheet(807/1302 Pages) FREESCALE

807 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

15-29

The DMA controller supports misaligned transfers for both the source and destination addresses.

In order to maximize performance, the source and destination engines align the source and

destination addresses to a 64-byte boundary. The DMA always reads/writes the maximum number

of bytes for a given transfer as described by the capability inputs of the DMA controller except for

globally coherent transactions that use the size of the cache coherence granule as described by the

mode select input. Using 256 bytes over the RapidIO interface reduces packet overhead which

translates to increased bandwidth utilization through the interface.

The DMA controller supports bandwidth control, which prevents a channel from consuming all

the data bandwidth in the controller. Each channel is allowed to consume the bandwith of the

shared resources as specified by the bandwidth control value. After the channel uses its allotted

bandwidth, the arbiter grants the next channel access to the shared resources. The arbitration is

round robin between the channels. This feature is also used to implement the external control

pause feature. If the external control start and pause are enabled in the MRn, the channel enters a

paused state after transferring the data described in the bandwidth control. External control can

restart the channel from a paused state.

The DMA controller is designed to support RapidIO transaction types, including various priority

level support. The DMA controller offers additional features from previous generations in which

the reads can be mapped to globally coherent (IO_READ), non-coherent (NREAD), or

maintenance reads. In addition, the writes can be mapped to coherent (flush with data) and

non-coherent (NWRITE, NWRITE_R) writes, messages, and maintenance writes.

The DMA programming model permits software to program each DMA engine independently to

interrupt on completed segment, chain, or error. It also provides the capability for software to

resume the DMA engine from a hardware halted condition by setting the channel continue bit,

MRn[CC]. See Table 15-21 on page 15-36 for more complete descriptions of the channel states

and state transitions.

15.4.1.1 Basic DMA Mode Transfer

This mode is primarily included for backward compatibility with existing DMA controllers which

use a simple programming model. This is the default mode out of reset. The different modes of

operation under the basic mode are explained in the following sections.

15.4.1.1.1 Basic Direct Mode

In basic direct mode, the DMA controller does not read descriptors from memory, but instead uses

the current parameters programmed in the DMA registers to start the DMA transfer. Software is

responsible for initializing SARn, SATRn, DARn, DATRn, and BCRn registers. The DMA

transfer is started when MRn[CS] is set. Software is expected to program all the appropriate

registers before setting MRn[CS] to a 1. The transfer is finished after all the bytes specified in the

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