MPC8540 datasheet(804/1302 Pages) FREESCALE

804 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

15-26

Freescale Semiconductor

DMA Controller

Table 15-18 describes the fields of the SSRn.

15.3.2.13 Destination Stride Registers (DSRn)

The destination stride register contains the stride size, and distance. Note that the destination stride

information is loaded when a new list descriptor is read from memory. Therefore, the destination

stride register is applicable for all link descriptors in the new list. Changing the destination stride

information for a link requires that a new list be generated. Figure 15-20 describes the DSRn.

Figure 15-20. Destination Stride Registers (DSRn)

Table 15-19 describes the fields of the DSRn.

15.3.2.14 DMA General Status Register (DGSR)

The DMA general status register combines all of the status bits from each channel into one

the DGSR.

Table 15-18. SSRn Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–19

SSS Source stride size. Number of bytes to transfer before jumping to the next address as specified in the

source stride distance field.

20–31

SSD Source stride distance. The source stride distance in bytes from start byte to start byte.

R 0 00 00

DSS

DSD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_1144, 0x2_11C4, 0x2_1244, 0x2_12C4

Table 15-19. DSRn Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–19

DSS Destination stride size. Number of bytes to transfer before jumping to the next address as specified in

the destination stride distance field.

20–31 DSD Destination stride distance. The destination stride distance in bytes from start byte to start byte.

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